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Integrated Circuit Systems, Inc.
ICS843031
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
FEATURES
* 1 differential 3.3V LVPECL output * Crystal oscillator interface designed for 18pF parallel resonant crystals * Output frequency range: 290MHz - 350MHz * RMS phase jitter @312.5MHz (1.875MHz - 20MH * VCO frequency range: 580MHz - 700MHz * RMS phase jitter @312.5MHz (1.875MHz - 20MHz): 0.475ps (typical) RMS phase jitter @318.75MHz (1.875MHz - 20MHz): 0.475ps (typical) * 3.3V operating supply * 0C to 70C ambient operating temperature * Lead-Free package RoHS compliant
GENERAL DESCRIPTION
The ICS843031 is a 1 Gigabit Ethernet Clock Generator and a member of the HiPerClocksTM HiPerClockSTM family of high performance devices from ICS. The ICS843031 can synthesize 1 Gigabit Ethernet, SONET, or Serial ATA reference clock frequencies with the appropriate choice of crystal and output divider. The ICS843031 has excellent phase jitter performance and is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space.
ICS
FREQUENCY TABLE
Inputs Crystal Frequency (MHz) 25.92 26.04166 26.5625 M/N Ratio (Multiplier) 12 12 12 Output Frequency (MHz) 311.04 312.5 318.75
BLOCK DIAGRAM
PIN ASSIGNMENT
VCC XTAL_OUT XTAL_IN VEE 1 2 3 4 8 7 6 5 Q0 nQ0 VCC PWR_DN
XTAL_IN
OSC
XTAL-OUT
Phase Detector
VCO
/2
nQ0 Q0
ICS843031
8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View
/24 (fixed)
PWR_DN
843031AG
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REV. A MARCH 31, 2005
Integrated Circuit Systems, Inc.
ICS843031
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
Type Power Input Power Input Pullup Description Core supply pin. Cr ystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Negative supply pin. Output state control input. High impedance when LOW (oscillator stops). LVCMOS/LVTTL interface levels. Differential clock outputs. LVPECL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 6 2, 3 4 5 7, 8 Name VCC XTAL_OUT, XTAL_IN VEE PWR_DN nQ0, Q0
Output
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characterristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP Parameter Input Capacitance Input Pullup Resistor Test Conditions Minimum Typical 4 51 Maximum Units pF k
843031AG
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REV. A MARCH 31, 2005
Integrated Circuit Systems, Inc.
ICS843031
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
4.6V -0.5V to VCC + 0.5V 50mA 100mA 101.7C/W (0 mps) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V5%, TA=0C TO 70C
Symbol VCC IEE Parameter Core Supply Voltage Power Supply Current PWR_DN = 1 PWR_DN = 0 Test Conditions Minimum 3.135 Typical 3.3 Maximum 3.465 105 <1 Units V mA mA
TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = 3.3V5%, TA=0C TO 70C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current PWR_DN PWR_DN VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V -150 Test Conditions Minimum 2 -0.3 Typical Maximum VCC + 0.3 0.8 5 Units V V A A
TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = 3.3V5%, TA=0C TO 70C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCC - 1.4 VCC - 2.0 0.6 Typical Maximum VCC - 0.9 VCC - 1.7 1.0 Units V V V
NOTE 1: Outputs terminated with 50 to VCC - 2V.
843031AG
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REV. A MARCH 31, 2005
Integrated Circuit Systems, Inc.
ICS843031
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
Test Conditions Minimum 12 Typical Fundamental 40 50 7 1 MHz pF mW Maximum Units
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V5%, TA=0C TO 70C
Symbol fOUT Parameter Output Frequency RMS Phase Jitter (Random); NOTE 1 Output Rise/Fall Time 312.5MHz, Integration Range: 1.875MHz to 20MHz 318.75MHz, Integration Range: 1.875MHz to 20MHz 20% to 80% Test Conditions Minimum 290 0.475 0.475 200 46 600 54 Typical Maximum 350 Units MHz ps ps ps %
tjit(O)
tR / tF
odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plot.
843031AG
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REV. A MARCH 31, 2005
Integrated Circuit Systems, Inc.
ICS843031
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
TYPICAL PHASE NOISE AT 312.5MHZ
0
-30 -40 -50 -60 -70 -80 -90 -100
1 Gigabit Ethernet Filter 312.5MHz
RMS Phase Jitter (Random) 1.875Mhz to 20MHz = 0.475ps (typical)
-10 -20
NOISE POWER dBc Hz
Raw Phase Noise Data
-110 -120 -130 -140 -150 -170 -180 -190 100 1k -160
10k
Phase Noise Result by adding 1 Gigabit Ethernet Filter to raw data
100k 1M 10M 100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 318.75MHZ
0
-30 -40 -50
1 Gigabit Ethernet Filter 318.75MHz
RMS Phase Jitter (Random) 1.875Mhz to 20MHz = 0.475ps (typical)
-10 -20
NOISE POWER dBc Hz
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150
Raw Phase Noise Data
100 1k 10k
-160 -170 -180 -190
Phase Noise Result by adding 1 Gigabit Ethernet Filter to raw data
100k 1M 10M 100M
OFFSET FREQUENCY (HZ)
843031AG
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REV. A MARCH 31, 2005
Integrated Circuit Systems, Inc.
ICS843031
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
2V
LVPECL
nQx
Noise Power
VCC
Qx
SCOPE
Phase Noise Plot
Phase Noise Mask
VEE
f1 Offset Frequency f2
-1.3V 0.165V
RMS Jitter = Area Under the Masked Phase Noise Plot
3.3V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
nQ0 Q0
Pulse Width t
PERIOD
80% Clock Outputs
80% VSW I N G
20% tR tF
20%
odc =
t PW t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
843031AG
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REV. A MARCH 31, 2005
Integrated Circuit Systems, Inc.
ICS843031
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR APPLICATION INFORMATION
CRYSTAL INPUT INTERFACE
The ICS843031 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 1 below were determined using a 26.04167MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts.
XTAL_OUT C1 12p X1 18pF Parallel Cry stal XTAL_IN C2 12p
Figure 1. CRYSTAL INPUt INTERFACE
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines.Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50 FOUT FIN
125 Zo = 50 FOUT
50 50 VCC - 2V RTT
125
Zo = 50
FIN
Zo = 50 84 84
1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o
FIGURE 2A. LVPECL OUTPUT TERMINATION
843031AG
FIGURE 2B. LVPECL OUTPUT TERMINATION
REV. A MARCH 31, 2005
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Integrated Circuit Systems, Inc.
ICS843031
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843051. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS843051 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_TYP = 3.465V * 105mA = 363.83mW Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 363.8mW + 30mW = 393.8mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.394W * 90.5C/W = 105.65C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA
FOR
8-PIN TSSOP, FORCED CONVECTION
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 101.7C/W
1
90.5C/W
2.5
89.8C/W
843031AG
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REV. A MARCH 31, 2005
Integrated Circuit Systems, Inc.
3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 4.
VCC
ICS843031
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
Q1
VOUT RL 50 VCC - 2V
FIGURE 3. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = V (V
CCO_MAX
OH_MAX
=V
CC_MAX
- 0.9V
-V
OH_MAX
) = 0.9V =V - 1.7V
*
For logic low, VOUT = V (V
CCO_MAX
OL_MAX
CC_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V
OH_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OH_MAX
) = [(2V - (V
CC_MAX
-V
OH_MAX
))/R ] * (V
L
CC_MAX
-V
OH_MAX
)=
[(2V - 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
843031AG
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REV. A MARCH 31, 2005
Integrated Circuit Systems, Inc.
ICS843031
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR RELIABILITY INFORMATION
TABLE 7.
JAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP
JA by Velocity (Meters per Second)
0 1
90.5C/W
2.5
89.8C/W
Multi-Layer PCB, JEDEC Standard Test Boards
101.7C/W
TRANSISTOR COUNT
The transistor count for ICS843031 is: 2360
843031AG
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REV. A MARCH 31, 2005
Integrated Circuit Systems, Inc.
ICS843031
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
8 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 8. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 2.90 6.40 BASIC 4.50 Millimeters Minimum 8 1.20 0.15 1.05 0.30 0.20 3.10 Maximum
Reference Document: JEDEC Publication 95, MO-153
843031AG
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REV. A MARCH 31, 2005
Integrated Circuit Systems, Inc.
ICS843031
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
Marking 3031A 3031A TBD TBD Package 8 lead TSSOP 8 lead TSSOP 8 lead "Lead-Free" TSSOP 8 lead "Lead-Free" TSSOP Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS843031AG ICS843031AGT ICS843031AGLF ICS843031AGLFT
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockSTM and FemtoClocksTM are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843031AG
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REV. A MARCH 31, 2005

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